By Inc. Apple Computer
The interior tale on Macintosh expertise This booklet offers distinctive details at the expertise that has been utilized in Apple desktops for years and is now a part of the Apple/IBM/Motorola universal structure. It explains a number of the uncomplicated layout ideas that experience contributed to the mythical Macintosh functionality and straightforwardness of use. Written for desktop execs, this ebook comprises sufficient aspect for engineers and architects to copy many Macintosh positive aspects and modes of operation. a lot of the technical details incorporated is released right here for the 1st time. The Apple applied sciences for which this publication presents layout information contain: The Mac I/O Chip: an built-in circuit that offers computing device designers the various significant Macintosh I/O positive factors in a single package deal The Apple machine Bus: an easy connection ability for consumer interface units comparable to keyboards and mice Macintosh more desirable SCSI undefined: a flexible controller for the Small laptop process Interface bus Descriptor-Based Direct reminiscence entry: an easy but effective method for transporting facts to and from peripheral units Miscellaneous Apple applied sciences together with: the Macintosh serial port, the Toolbox ROM, Macintosh Open Firmware, NVRAM, and gear keep watch over An appendix describes Apple's courses for builders and explains how you can start designing Macintosh-compatible items for the typical Reference Platform.
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Additional info for MacIntosh Technology in the Common Hardware Reference Platform
The response time is set by the value in bits [10:9] of the PCI bus status register (see “Device Status” beginning on page 39). This field is read-only; its value indicates the maximum response time, as shown in Table 11. Table 11. Device response times [10:9] Value Response Time, Cycles 0x0 1 0x1 2 0x2 3 0x3 Reserved 30 Chapter 2 The Mac I/O Chip The MIO chip will respond in 2 cycles to all PCI bus transactions, and bits [10:9] in the PCI bus status register will always return 0x0. 2 Data Transactions The PCI bus interface on the MIO chip is idle when PciFrame_L and PciIRdy_L are both negated.
Table 9 describes its bits. Table 9. Feature Control register Bit Name Description Default 0 SCC_CELL_EN Stops the SCC clock when low. Software must guarantee that DMA transactions are finished. 1 1 SCSI_CELL_EN Stops the SCSI clock when low. Software must guarantee that DMA transactions are finished. 7 27 General Functions Table 9. Feature Control register (continued) Bit Name Description SccAEnable Enables the SCC outputs TXDA, RTSA_L, and DTRA_L, which are tristated when SccAEnable is low. The following 1 inputs are blocked when SccAEnable is low: GPIOA_L (forced high), TRXCA (forced low), and RXDA (forced low).
The cache ID ROM contains cache size information, which power-on self-test (POST) routines may use to test the cache SIMM. It also contains timing information for the SIMM. The contents of the cache ID ROM are specified by the SIMM designer. The interface to the cache ID ROM consists of the lines SCLK and SDAT, which use two of the four CachePD pins shown in Table 45, beginning on page 72. All four pins must be pulled high on the motherboard. If any of the four pins are low, it indicates that a cache is present and gives static configuration information.