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It is also permissible to inter-mix the or-separators and comma-separators in the same list, but this style is discouraged, as it would make the source code confusing to read. Synthesis considerations This enhancement should be synthesizable. 28 Verilog-2001: A Guide to the New Features of the Verilog HDL 11. Combinational logic sensitivity lists Background In hardware, combinational logic outputs reflect the values of the inputs to that block of logic. There is no storage in combinational logic, so each time any input changes, the output may be affected.
Synthesis considerations This enhancement may not be synthesizable. Most current synthesis tools have limited support for signed operations. 44 Verilog-2001: A Guide to the New Features of the Verilog HDL 19. Signed based integer numbers Background In Verilog-1995, a literal integer number can be specified in three ways:
The starting address can be any constant expression; there does not need to be an address zero. The ending address must also be a constant expression, and can be smaller or greater than the starting address. Once an array is declared, a full word from the array can be selected, using an index. The index can be constant or variable. For example: data = RAM; RAM [address_bus] //read word at index 100 data; //write to word at index of address bus value Verilog-1995 does not permit accessing a bit-select or part-select from within an array.