Advances in Electronic Testing: Challenges and Methodologies by Dimitris Gizopoulos

By Dimitris Gizopoulos

This is a brand new form of edited quantity within the Frontiers in digital checking out ebook sequence dedicated to fresh advances in digital circuits trying out. The booklet is a finished elaboration on very important themes which seize significant examine and improvement efforts at the present time. "Hot" issues of present curiosity to check expertise neighborhood were chosen, and the authors are key participants within the corresponding topics.

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Path Delay Faults A path delay fault assumes that a logic transition is delayed along an entire path. A gate delay fault can be thought of as a path delay fault through a single gate. Consider the path from A through D, H and I to J in Figure 1-21. E=0 G A C 0 I D B=1 H F=0 Figure 1-21: Example circuit for path delay faults. J 26 Chapter 1 – Defect-Oriented Testing As the rising transition moves through the circuit, it will be delayed. If the signal is delayed beyond the sampling time at J (say a clock edge at a flip-flop), then a delay fault has occurred along that path.

These have the property that they result in timing related failures at low operating frequency, but not high frequency. Originally, bridging faults were considered to have zero resistance. Later resistance models were added. Now, defect capacitance must also be considered. Intuitively, the increasing importance of wire capacitance in delay calculations is due to the increasing relative capacitance of wiring versus gates as a result of CMOS scaling. In order to measure timing behavior accurately, parasitic capacitances between wires must now be extracted for almost all designs.

35u level and below, however, it became clear that IDDQ testing was becoming increasingly difficult, and 14 15 16 Fault grading is the process of simulating faults to determine fault coverage. An n-detect test set forces each fault to be detected n different ways rather than just once. Current-based testing looks for defects in larger areas than a node which voltage-based tests examine. 30 Chapter 1 – Defect-Oriented Testing that the line between good and bad parts was increasingly difficult to draw (see the histogram of Figure 1-24 [25]).

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